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october 2012 doc id 023314 rev 1 1/39 AN4129 application note steval-ill044v1: 9 w triac dimmable, high power factor, isolated led driver based on the hvled815pf (for us market) by thomas stamm introduction the steval-ill044v1 demonstration board showcases st's new led driver chip, the hvled815pf. it solves the problem of low-cost drive circuitry for led replacements for 40 to 60 watt incandescent or equivalent compact-fluorescent lamps. the hvled815pf is a new integrated power controller using primary-side control to achieve led current regulation within +/-5%. (it also has primary-side voltage regulation, used here for open load protection.) the device incorporates an 800 v avalanche-rated fet and fits in a standard so-16 package. an internal startup circuit eliminates the need for external rapid-start circuitry. the pfc-flyback power converter operates in transition mode for highest efficiency and best use of components. with the addition of a few extra components the hvled815pf is made to draw near-sinusoidal input current from the ac line. the circuit regulates led current over a wide range of line voltage and led string voltage, and is dimmable with standard triac-based dimmers. figure 1. image of top and bottom view www.st.com
contents AN4129 2/39 doc id 023314 rev 1 contents 1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 transition mode flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.2 pfc-flyback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.3 primary side control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4 using the hvled815pf current limit for power factor correction . . . . . . . 7 2.4.1 average current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.4.2 adding an ac component to the current regulator . . . . . . . . . . . . . . . . . . 8 3 power converter performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 output current regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 problem - low line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.4 addition of diode clamp to limit input current . . . . . . . . . . . . . . . . . . . . . . 13 3.5 dimmed performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.6 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 circuit description and design guidance . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 the load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 preload resistor (r9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 output filter capacitor (c11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 led ripple current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.2 allowable ripple current in leds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.4 diode selection (d3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.1 speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.2 reverse voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.4.3 current rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.5 snubber capacitor selection (c10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6 transformer design (t1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.1 operating frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.2 primary peak current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4.6.3 reflected voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN4129 contents doc id 023314 rev 1 3/39 4.6.4 primary inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.5 leakage inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.6 auxiliary winding turns ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6.7 final transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.7 dmg pin (r6, r7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.8 filter capacitor for vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.9 comp pin capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.10 current sense resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4.11 ac injection divider (r3, r4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.12 emi filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.12.1 supporting the flyback input current . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.13 emi filter and dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.13.1 damping the input filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.14 emi plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.15 startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.16 component stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.16.1 thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.16.2 electrical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.17 extensions and modifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.17.1 lower output voltage, higher current . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.17.2 emi filter alternatives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.17.3 higher line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5 bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6 transformer specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 pc layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of figures AN4129 4/39 doc id 023314 rev 1 list of figures figure 1. image of top and bottom view. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. physical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. fet drain voltage waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 4. distortion of input current with sinewave reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 5. current distortion with sinewave input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 6. voltage and current waveforms with ac injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 7. waveforms with 90 v input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 8. waveforms with 110 v input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 9. waveforms with 130 v input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 10. power factor vs. line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 11. thd vs. line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 12. led current vs. number of leds, line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 13. efficiency vs. number of leds, line voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 figure 14. power loss vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 15. power loss vs. sinusoidal input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 16. output current vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 17. thd vs. input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 18. 70 vrms input, no diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 19. 70 vrms input, 1n4148, ~0.6 v drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 20. 70 vrms input, bat48, ~0.3 v drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 21. 40 vrms dimmed input, no diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 22. 40 vrms dimmed input, bat48 diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 23. power loss vs. dimmed rms line voltage (120 v line) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 24. dimmed efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 25. output current vs. dimmed rms line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 26. nema limits, incandescent light, led relative current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 27. schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 28. led dynamic resistance vs. current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 29. simplified lisn schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 30. conducted emi limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 31. input emi filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 32. flyback converter input current waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 33. undamped input filter waveforms with triac dimmer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 34. properly damped waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 35. final input filter design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 36. input transient at 200 ma/div, 2.5 ms/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 37. input transient at 500 ma/div, 500 s/div . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 38. input transient at 1 a/div, 50 s/div. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 39. conducted emi, peak hold for 10 scans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 40. cold startup, input and led currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 41. voltage and current stress . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 42. transformer specifications for 18-led load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 43. top placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 44. top copper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 45. bottom placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 46. bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AN4129 features doc id 023314 rev 1 5/39 1 features the demonstration board features are: +/- 5% primary-side current regulation, no optocoupler fully isolated output low component count - 27 parts, including the emi filter only 1 tight-tolerance component high efficiency, >86% high power factor >0.98 low thd, <20% over 90 v to 132 v range fits in 28 mm tubing 9 w output, for light equal to 40-60 w incandescent startup within 0.2 seconds dimmable over 90 v to 132 v range. figure 2. physical
theory of operation AN4129 6/39 doc id 023314 rev 1 2 theory of operation 2.1 transition mode flyback flyback power converters operate by storing energy from the primary side in an inductor's air gap, and discharging the energy into a load on the secondary side. the converter can run in two modes: 1. discontinuous conduction, where there is a deadtime between discharge and charge cycles. 2. continuous conduction, where the discharge cycle is ended by starting the charge cycle before all the stored energy is delivered to the load. neither mode fully utilizes the magnetic structure of the inductor. however, if the recharge cycle is started just after the discharge cycle ends, the natural ringing of the inductor and stray capacitance can be used to reduce turn-on voltage stress on the switch. transition mode converters can be very efficient as a result, having greatly reduced turn-on loss - the switch does not have to discharge its own and stray capacitance from a high voltage. figure 3. fet drain voltage waveforms operating frequency is a function of source and load voltages, and load current. if the source voltage varies, the operating frequency varies. this makes the transition mode converter very popular in low-cost commercial applications, where the varying frequency due to input voltage ripple spreads noise over a wide spectrum, reducing the noise at any one frequency. conducted emi tests can be easier to pass.
AN4129 theory of operation doc id 023314 rev 1 7/39 2.2 pfc-flyback in the pfc-flyback converter the input voltage is the rectified line voltage, with almost no filtering. converter input voltage goes to zero when the line voltage crosses zero. it's common practice to use the rectified line voltage as a reference for the peak current in the flyback converter's switch. this does not result in sinusoidal input current, but it is close enough. the duty cycle change with input voltage still distorts the waveform. this is discussed in detail in st's an1059 application note. figure 4. distortion of input current with sinewave reference 2.3 primary side control a pfc-flyback converter usually uses a pfc controller chip such as st's l6562at with an external fet and a feedback loop. the secondary side voltage and/or current are monitored, compared to a reference on the secondary side, and a control signal sent to the primary side with an opto-isolator. this signal is multiplied by a reference waveform (the rectified line voltage) and used to control peak switch current. st has developed a primary-side control circuit that eliminates the need for the secondary- side components. voltage is monitored on the housekeeping winding at the end of the flyback converter's discharge cycle, just as the secondary current reaches zero. secondary current is set by measuring duty cycle and adjusting peak primary current, to provide a calculated secondary average current. but the circuit cannot work with a multiplier, so another method of shaping the peak switch current waveform must be found. 2.4 using the hvled815pf current limit for power factor correction 2.4.1 average current regulation the hvled815pf does an excellent job of regulating output current in a dc input flyback supply. it calculates the peak current at which to shut off the driving fet by looking at the duty cycle continuously. the error between desired duty cycle and actual duty cycle appears as a current on the iled pin - a capacitor on this pin integrates the error to zero over time. since the voltage on this pin, divided by 2, directly sets the current at which the fet switch turns off, the output current is regulated. 2ectifiedlinevoltage #o rrespondinginputcurrent !-v
theory of operation AN4129 8/39 doc id 023314 rev 1 in dc input flyback power supplies a very small capacitor is normally used on the iled pin for quick response to changing load or input voltage. in the led driver application the capacitor on this pin can be much larger, regulating led current more slowly, averaging the error out over several cycles of input voltage. a 4.7 f low voltage ceramic capacitor is used. the average led current is kept constant even if the input voltage waveform is grossly distorted, such as a rectified sinewave, as occurs in the pfc-flyback topology. the input current waveform, however, is truly ugly. check out the magenta trace in the figure below. figure 5. current distortion with sinewave input where: yellow = line voltage magenta = line current. the peak fet shut-off current remains at the same level throughout the ac half cycle, but the duty cycle of the converter changes. (fet on-time increases at lower input voltage - it takes longer to reach the same current if the converter input voltage is lower). the resulting input current waveform is very rich in harmonics (thd is in the range of 130%), though power factor is actually quite good. 2.4.2 adding an ac component to the current regulator if an ac signal is injected into the iled pin, the instantaneous fet peak current can be controlled, while the average output current (a dc level) remains regulated. the figure below shows the injection of a small fraction of the line voltage into the bottom of the iled capacitor. the change in the input current waveform is dramatic. but it is best for only one line voltage, and is a compromise for all others. but it is ?good enough?. the small capacitor across the lower resistor is only there to keep switching noise out of the circuit.
AN4129 theory of operation doc id 023314 rev 1 9/39 figure 6. voltage and current waveforms with ac injection the current waveform at ?nominal line? above, actually has the lowest harmonic content due to the input current distortion inherent in the pfc-flyback converter. the hvled815pf clamps the voltage on the iled pin between about 0.2 v on the low end, and at about 1.5 v on the high end. if the injected waveform wants to swing below 0.2 v, the peak current in the fet is set to zero, so no input current flows. figure 9. waveforms with 130 v input :ero $#levelneeded tode liver u& n& + + !ppx6 ,ow,ine .ominal,ine (igh,ine ),%$ 0). !ppx6 6ery,ow,ine 2ectified,ine :ero :ero :ero !ppx6 !ppx6 3inewave2eference )nput#urren t correctloadcurrent (6,%$0& !-v figure 7. waveforms with 90 v input figure 8. waveforms with 110 v input
theory of operation AN4129 10/39 doc id 023314 rev 1 where: yellow = line voltage magenta = line current, 50 ma/div ref -3div blue = voltage at i led pin, ref -3div green = led current, 50 ma/div ref -3div. wide-range operation at line voltages in the 230 v range, the input current resembles that of a capacitor input filter - pulses in the middle of the ac half cycle, with correspondingly high thd and poor power factor. but the converter works, quite well, over the wide line voltage range of 90 v to 305 v. figure 10 shows power factor to be excellent over the wide voltage range, typically well above 0.98. placement of the emi filter after the rectifier reduces the phase shift component of power factor to near zero, and the current waveform is nearly sinusoidal. however, total harmonic distortion ( figure 11 ) reaches a minimum at only one line voltage. the industry standard for thd is 20% maximum, ruling out the use of this design for wide- range line. figure 10. power factor vs. line voltage figure 11. thd vs. line voltage !-v !-v
AN4129 power converter performance doc id 023314 rev 1 11/39 3 power converter performance 3.1 output current regulation performance of the power converter is excellent over a very wide range of load conditions, even with the ac injection. (data was taken only over the intended 120 v ac input operating range, 90 v to 132 v.) two limiting factors can be seen in figure 12 , below: voltage limiting reduces led current at about 21 leds, corresponding to about 66 v. the limit was imposed to protect the output capacitor, rated for 63 v. peak current limiting is evident at 90 v input - the line current exceeds the limit when high output power is required. the diode limiter (see section 3.4 ) is in action at 90 v input above about 13 leds, 40 v. figure 12. led current vs. number of leds, line voltage 3.2 efficiency as expected, efficiency ( figure 13 ) drops off at low voltages. the sharp step between 10 and 12 leds is due to the auxiliary winding. below this point, the converter is powered by the hvled815pf's internal startup circuit, a lossy series regulator, directly from the input line - the reflected led voltage on the auxiliary winding is too low to power the chip. above this point, the downslope is due to a small amount of power wasted in the chip from higher reflected led voltage, but this margin is required for dimming operation. ? e ? ? ? ? ? ?? k?????v? eu?}(>? ?s s s ?s ??s !-v
power converter performance AN4129 12/39 doc id 023314 rev 1 figure 13. efficiency vs. number of leds, line voltage note that operation was erratic around the step. at low line the converter may stop operation or cause the leds to blink. led loads should be coordinated with the transformer turns ratio (secondary to auxiliary winding) to avoid this region. 3.3 problem - low line voltage since the unit regulates output current, if the line voltage drops it draws increased line current to maintain the output current. the increase in input current leads to efficiency reduction due to i 2 r losses, particularly in the hvled815pf's internal fet. a plot of power loss vs. line voltage shows unacceptable losses below about 80 v input. figure 14. power loss vs. input voltage in a dc-input converter a ?brownout? circuit is generally used to turn the converter off at low line voltage. but in a pfc converter the input voltage goes below the brownout level twice per cycle. clearly the unit cannot be used below about 80 v without some kind of protection. the bulk of the increase is dissipation in the hvled815pf's internal fet. thermal runaway results if this is not controlled. x9 ?x9 x9 ?x9 ?x9 ??x9 ?x9 ? ? ? ?? ((]]v?u9 eu?}(>? ?s s s ?s ??s !-v 3rzhu/rvv:dwwv ,qsxw9506 !-v
AN4129 power converter performance doc id 023314 rev 1 13/39 3.4 addition of diode clamp to limit input current since the peak fet current is directly controlled by the voltage on the iled pin, a diode clamp can be added to limit the voltage increase to reasonable levels. the graph below shows the results for two diode types, a fast p-n diode having about 0.6 v forward drop, and a schottky diode having about 0.3 v forward drop, placed across the dc filter capacitor. figure 15. power loss vs. sinusoidal input voltage the input current increase can now be limited to a reasonable value. there are two consequences of this addition: line regulation is lost at low input voltages (the iled pin cannot rise to regulate current). figure 16. output current vs. input voltage and thd is significantly improved at low input voltage: figure 17. thd vs. input voltage x) q) . . ,/(' 3,1 5hfwlilhg/lqh +9/('3) ',2'( 3rzhu/rvv:dwwv ,qsxw9506 1r'lrgh 1 %$7 !-v /('&xuuhqwp$ ,qsxw9upv 1r 'lrgh 1 %$7 !-v 7rwdo+duprqlf'lvwruwlrq ,qsxw9upv 1r'lrgh 1 %$7 !-v
power converter performance AN4129 14/39 doc id 023314 rev 1 the scope shots below show the result on the input current waveform. figure 20. 70 vrms input, bat48, ~0.3 v drop figure 18. 70 vrms input, no diode figure 19. 70 vrms input, 1n4148, ~0.6 v drop trace colors: yellow = line voltage magenta = line current, 50 ma/div ref -3div blue = voltage at i led pin, ref -3div green = led current, 50 ma/div ref -3div trace colors: yellow = line voltage magenta = line current, 50 ma/div ref -3div blue = voltage at i led pin, ref -3div green = led current, 50 ma/div ref -3div
AN4129 power converter performance doc id 023314 rev 1 15/39 3.5 dimmed performance the diode-improved waveform also helps when the circuit is dimmed with a triac, especially at low conduction angles. the iled pin voltage is not allowed to rise. note how high the iled pin voltage (green trace) has risen in figure 21 , compared to figure 22 , as the chip attempts to regulate the output current. the voltage on that pin directly controls the peak fet current. where: yellow = line voltage magenta = line current blue = ac injection voltage green = voltage at iled pin. the magenta trace, input current, is greatly improved. the input current now tracks the input voltage, instead of rising as duty cycle becomes larger near the end of the ac cycle. dissipated power is also reduced at low conduction angles due to the lower rms input current: figure 23. power loss vs. dimmed rms line voltage (120 v line) figure 21. 40 vrms dimmed input, no diode figure 22. 40 vrms dimmed input, bat48 diode 3rzhu/rvv:dwwv 'lpphg506/lqh9rowdjh 1r 'lrgh 1 %$7 !-v
power converter performance AN4129 16/39 doc id 023314 rev 1 efficiency is plotted for only the bat48 case: figure 24. dimmed efficiency the diode also reduces led current at low conduction angles. figure 25. output current vs. dimmed rms line note that the dimming curve for the schottky diode unit is much smoother and slightly lower at the low end. this allows the unit to meet the dimming requirements of nema ssl 6-2010, as shown below. figure 26. nema limits, incandescent light, led relative current 3.6 summary performance is excellent for an isolated led driver of this size and simplicity. the added bonuses of dimmability and power factor correction compel consideration of the design. %fficiency $immed 2-3 line voltage !-v ,%$current $immed2-3linevoltage .odiode . "!4 !-v 2elative output $immed 2-3 input voltage 33, a lower limit 33, a upper limit )ncandescent relative output 2elative dimmed output #urrent !-v
AN4129 power converter performance doc id 023314 rev 1 17/39 figure 27. schematic note: the fusible resistor (r1) in the bill of materials has been tested for long periods at a conduction angle of 90 degrees (w orst stress point) and is known to hold. test substitutes carefully. !-v # u &6 32# ),%$ $-' #/-0 .! $rain $rain #3 6cc '.$ $rain $rain .! .# .! .! 5 (6, %$ 0& 2 + 2 + 2 2 ,%$ ,%$7(4 ,%$ ,%$7(4 !average !ppx6 # p&9 !# 6 !# 6 "2 "2 ) $' %3 -4 # n& 3eenote 2 /hm&usible , . 4 $ --3$ 6 4 #ramer#3- 6 6refl 6refl 6 ,prim(y # u&6 $ 344(! # u&6 # n& 2 + 2 + $ "!4:&),- # u&6 2 7 2 + .eeded onlyfor /60 optional # p& # u& 6 # u&6 2 + 2 + , m(y , m(y ,%$s )r ms ! )p k ! )rms ! )pk !
circuit description and design guidance AN4129 18/39 doc id 023314 rev 1 4 circuit description and design guidance this section, like any power design, proceeds from output to input. please refer to the schematic on the previous page. 4.1 the load the converter design is optimized for a string of 18 leds, about 54 vdc at a current of 175 ma. 4.2 preload resistor (r9) while the unit's dimmed output current lies inside the nema limits, performance can be improved by adding a light preload. this reduces efficiency, but the unit's operation is much more stable at low conduction angles. the reason is that most dimmers rely on line voltage to set the triac firing delay after the zero crossing. at low conduction angles the delay is strongly dependent on line voltage - the slightest variation is visible because the led light output reacts much more quickly to current changes than do incandescent lamps. the filament is a thermal reservoir, slowing the lamp's response to changes in the dimmed rms input voltage. the preload resistor is also required for the open load protection to work. without it, the output voltage climbs until the leakage current in the output filter capacitor limits it. this causes no damage short-term, but should be avoided. 4.3 output filter capacitor (c11) 4.3.1 led ripple current leds require more filtering than normal loads. leds are diodes, and their impedance is a function of the current through them. typically, an led has a dynamic impedance, or slope resistance, of about 1/10 of the ratio of dc voltage to dc current.
AN4129 circuit description and design guidance doc id 023314 rev 1 19/39 figure 28. led dynamic resistance vs. current for a small voltage change the current change is about 10 times as large as for a resistive load. a 1 w white led (~3.2 v at ~350 ma) has a slope resistance of about 1 at full power. as the current is reduced, the led impedance rises accordingly, inversely proportional to the current. but the capacitor impedance determines the ripple voltage - the led current ripple percentage does not increase as the unit is dimmed. 4.3.2 allowable ripple current in leds at the converter switching frequency the output filter capacitor takes almost all the ripple current. the esr of the capacitor is dominant at that frequency, and is orders of magnitude lower than the led impedance. high frequency ripple in the leds is not a concern. at twice the line frequency (120 hz) led ripple can have an effect on people even if it can't be directly observed. it's common practice in the lighting industry to limit the optical ripple to about 10% rms of the total light, and nema ssl6-2010 requires a statement of ripple percentage on the sale package if this is exceeded. so led current ripple must be kept below 10%. at 120 hz capacitive reactance dominates the shunting impedance - esr can be ignored. because of the low led impedance the filter capacitors must reduce rms ripple voltage to about 1% of the led string voltage. equation 1 for this design, with (18) 3.2 v leds at 175 ma, the capacitance should be about 284 f. the value used was 330 f. !-v 'lrgh &xuuhqw 'lrgh9rowdjh /rz&xuuhqw g9 g,orz 9 9 9 g9 g,kljk 5dwhg&xuuhqw 6orsh 5hvlvwdqfh '\qdplf,pshgdqfh ri/('/rd g /('&kdudfwhulvwlf&xuyh c 0.707 100 i led ?? 2 120hz v string ?? -------------------------------------------------------- =
circuit description and design guidance AN4129 20/39 doc id 023314 rev 1 4.4 diode selection (d3) 4.4.1 speed d3 must be a fast-recovery part, but because of the transition mode topology the recovery requirements are modest. current in the diode reverses slowly, and the diode is thoroughly turned off well before the fet turns on. parts with trr up to about 70 ns are suitable. 4.4.2 reverse voltage the diode must support the reflected line voltage plus output voltage plus a small spike from leakage inductance. a standard 200 v fast-recovery diode was used. a high-voltage schottky diode would also work, with a slight gain in efficiency and slightly increased cost. 4.4.3 current rating this is a low-stress application for the diode. the 1-amp rating of st?s stth102a is probably too much, but the part is inexpensive, and it works well. 4.5 snubber capacitor selection (c10) the current at fet turn-off continues to flow in the leakage inductance of the transformer, resulting in a primary-side voltage spike. common practice is to use an rcd clamp or an rc snubber to dissipate this energy as heat. the snubber can be moved to the secondary side of the transformer if leakage inductance is low. the primary voltage can be caught on-the-rise by an r-c network placed across the secondary winding or the diode. this avoids the need for high-voltage diodes and capacitors on the primary side. experiments with relatively low values of capacitor and resistor determined that for a narrow range of capacitor values the primary overshoot at fet turn-off was greatly reduced. it was also discovered that the resistor is not needed if the secondary side capacitor is properly selected. criteria for selection have not been determined. it?s unnecessary for a 120 v line, but the chip was designed for the full line range of 90 v to 305 vac. 4.6 transformer design (t1) 4.6.1 operating frequency higher operating frequency reduces the size of the transformer. operating frequency can be increased up to the point where emi filtering requirements become the limiting factor. an operating frequency just below 150 khz puts the second harmonic inside the conducted emi band, but the harmonics are smaller and easier to filter than the fundamental. placing the fundamental at 120-135 khz at the nominal line voltage peak is a good compromise, considering component tolerances. 4.6.2 primary peak current this is set by the required output power, which is limited by the internal fet's on-resistance to about 10 w. for this design, at us mains voltage, the peak current is about 0.75 amps.
AN4129 circuit description and design guidance doc id 023314 rev 1 21/39 4.6.3 reflected voltage for pfc-flyback transition mode power converters on us 120 v lines the best reflected voltage choice is 110 to 130 v. this range gives the best converter efficiency. copper losses can be spread between the primary and secondary windings about equally, and the fet's turn-on losses discharging circuit capacitance are quite low. a turns ratio of 2:1 primary : secondary was selected, placing reflected voltage at about 112 v at full undimmed output. 4.6.4 primary inductance assuming the fet on-time takes up half the cycle time: equation 2 a value of 900 h was selected because additional time is required for the resonant drain voltage fall time of the transition mode converter. 4.6.5 leakag e inductance this should be as low as possible - energy stored here does not contribute to led power and must be dissipated as heat. the transformer used has about 8 h of leakage inductance, as seen from the primary winding. 4.6.6 auxiliary winding turns ratio operating voltage for the hvled815pf depends on the led voltage and this turns ratio. the led winding (secondary) voltage reflects to the flyback voltage on all windings. the turns ratio from the secondary to the auxiliary winding determines the auxiliary voltage, both for voltage regulation (open load protection) and for the vcc power supply. 4.6.7 final transformer specifications winding ratios, primary inductance, peak currents, and other specifications are shown in the schematic. the vendor's specification sheet appears in figure 42 . 4.7 dmg pin (r6, r7) this single pin performs several functions; voltage limiting, zero current detection, and correction for line voltage changes. its operation is discussed thoroughly in the datasheet and is only summarized here. the internal circuit is also used in st's hvled805 and altair chips. the datasheets and application notes for these parts can give additional insight into the pin operation. design begins with compensation for the internal comparator's propagation delay. at high line voltage the slope of fet current vs. time is higher, so for the same comparator reference voltage the current overshoots more than at low line. this is compensated by adding an offset proportional to line voltage to the comparator's reference input. r6, in conjunction with an internal resistor (rff) of about 45 , sets this compensation.
circuit description and design guidance AN4129 22/39 doc id 023314 rev 1 r6 and r7 form a divider that normally sets the converter output voltage. the led driver uses constant current mode - the constant-voltage circuit is used only for overvoltage protection, such as an open load situation. on the positive swing of the output and auxiliary windings the divided voltage is measured at the end of the transformer's discharge time, and compared to an internal 2.5 v reference by a transconductance op amp. the third function, zero current detection, uses the voltage at the dmg pin to determine the duty cycle of the output diode conduction period. this is used for the internal current regulator - the duty cycle measured here determines the fet cutoff current, indirectly controlling output current. the divider's resistor values have very little effect on this function. during product development, it is helpful to separate the functions. choose a value for r7 that sets the overvoltage protection level very high (2x expected), and adjust r6 to give the flattest current limit vs. line voltage characteristic. when the value for r6 is set, pick the value for r7 to give the correct overvoltage protection. 4.8 filter capacitor for vcc the dimming requirement sets a minimum size for this capacitor. during the dimmer's non- conducting period the line is not present for the internal startup circuit to take over, so the stored energy in this part is used to keep the chip alive. at low conduction angles the capacitor is barely topped off, and it must hold the vcc voltage above the shutoff threshold for a half cycle. at the same time, the leds are operating on very low current, and the reflected voltage is smaller than normal, and led dependent. the capacitor value therefore depends on the turns ratio of the auxiliary winding to the output winding, the led voltage at minimum conduction angle, and the shutoff threshold. a small 10 uf low voltage ceramic was tried, but the voltage coefficient of capacitance was so high that the part did not work in the dimming mode. capacitance was too low to maintain power to the chip between dimmed line pulses. high-k ceramic capacitance falls off dramatically well below the rated voltage. a 10 uf electrolytic was then selected and works well. its value can be increased quite a bit without affecting startup time - the charging of the output capacitor dominates the time from power application to first light. but 10 f is adequate. 4.9 comp pin capacitor because the hvled815pf is used only in current limit mode when driving leds, the usual loop stability compensation network is not needed. voltage limiting is used only when the led string is open (think bench testing?) and it needs to be small so that overvoltage response is quick. 1 nanofarad is a good value. 4.10 current sense resistor this resistor value is determined by the average led current desired and the turns ratio of the transformer, according to the following formula:
AN4129 circuit description and design guidance doc id 023314 rev 1 23/39 equation 3 where n is the transformer turns ratio, v cled is the internal reference, and r sense is the current sensing resistor. internally v cled is 0.2 v. this is the ideal situation. actually, because the transformer is not the ideal transformer, imperfect coupling makes the actual turn's ratio less than the designed value. also the voltage feed-forward compensation and demagnetizing time further reduces the actual led current from the calculated number. typically, the reduction factor (coefficient k in equation 4 below) is around 0.85~0.9. therefore, the formula to determine the resistor is: equation 4 for this demonstration board, with turns ratio of 2 and a 1.00 1% current sensing resistor, we get the led current around 180 ma. for different designs, small modifications may be needed, but once the final values are selected repeatability from unit to unit is excellent. 4.11 ac injection divider (r3, r4) in the us, total harmonic distortion (current) must be kept below 20% of the 60 hz fundamental. the input current is already distorted due to the use of a sinusoidal peak current envelope. input current harmonic distortion actually improves slightly when the line current goes to zero for a short time around the voltage zero crossing. the distortion minimum only occurs at one input voltage, increasing as the line voltage is moved away from that point. the average of the injected ac waveform (not the rms value) should be set approximately equal to the dc level required to give the correct current to the leds. at nominal line the average injected voltage is close to 0.95 v - the rms voltage is 1.111 times the average, or 1.05 v, peak voltage about 1.45 v. modifications may be necessary, but repeatability between units is excellent once the values are selected. there are two limits on the impedance of the network: loss in the divider (mostly the upper resistor), which affects efficiency impedance at the iref pin should be much lower than that of the internal duty cycle calculation circuitry. an upper divider resistance of 270 k keeps resistive loss low. equation 5 the efficiency reduction for this loss is 0.053 w/9.8 w = 0.54%. the impedance looking into the iled pin of the hvled815pf is approximately 1.5 v/ 10 a ? 150 k . this varies with duty cycle - it is lower as the line voltage is increased.
circuit description and design guidance AN4129 24/39 doc id 023314 rev 1 the injected voltage needed at the divider tap should be just sufficient to shut off the fet at the line zero crossing. the average of this voltage should therefore be equal to the average of an equivalent dc-input converter supplying the leds. the actual value of the lower resistor is determined experimentally to give the best compromise between high line and low line thd. with the 270 k upper divider resistor and the impedance of the iled pin in parallel, a 3 k resistor gives good results. thd is acceptable across the 90 v to 132 v voltage range. the divider values are not critical - 5% resistors are adequate. a small capacitor across the lower divider resistor smooths the current pulses from the duty cycle measurement circuitry and helps keep switching noise out of the system. this should be in the range of 10 nanofarads for the switching frequency used in the demo. 4.12 emi filter design in the us, conducted noise is measured between 150 khz and 30 mhz. low frequency noise is the most difficult to filter. the operating frequency was selected so that the fundamental is just below the measurement band, and the second harmonic frequency is as high as possible. the noise injected into the line can be broken into two components, differential mode and common mode. we consider the differential mode noise first. common mode noise is a very different problem. conducted emissions testing is done with a standard line impedance simulation network (lisn). a grossly simplified diagram is shown below. figure 29. simplified lisn schematic differential impedance in the noise spectrum (150 khz to 30 mhz) is 100 line-to-line, 50 line-to-ground. !-v (igh : (igh : , , ,).% .%542!, '2/5.$ # ,o w : # ,ow : /hms /hms '2/5.$
AN4129 circuit description and design guidance doc id 023314 rev 1 25/39 figure 30. conducted emi limits we design for peak noise at the fcc limit at 150 khz. the design leaves some margin due to the frequency selection. peak-to-peak of the 2 mvrms limit is about 6 mv per line relative to ground. the input filter is shown below. figure 31. input emi filter the typical differential filter consists of 4 components. starting at the noise source these are: shunt capacitor on the converter input (c1) series inductor l1 and l2 in series, or differential (leakage) inductance of a common mode choke shunt capacitor across line (c2) line impedance (in the lisn, about 100 line-to-line, 50 line-to-ground at measurement frequencies). 4.12.1 supporting the flyback input current first we consider the differential current drawn by the converter. the input current waveform at line peak is sketched below: d"u6m62-3?!2-3 d"u6m62-3?!2-3 d "u6m62-3?!2-3 d "u6m62-3?!2-3 d"u6m62-3?!2-3 k(z k(z -(z -(z 1uasi peaklimitline !veragelimitline d"perdecade !-v ' ' ' ' & x) & x) / p+\ 5 2kpv)xvleoh / p+\ 6,ine &xuuhqw6lqn frqyhuwhulqsxw !-v
circuit description and design guidance AN4129 26/39 doc id 023314 rev 1 figure 32. flyback converter input current waveform the peak current is about 0.7 a, and the on-time is about 3.5 microseconds. the charge that must be delivered by the capacitor directly across the converter each cycle is about: equation 6 the capacitance needed was determined experimentally - 0.1 f is a good starting point at this power level. so, ripple voltage for the 0.1 f capacitor is about: equation 7 values as small as 0.047 f can be made to work, but the inductor value must increase to keep the noise on the ac line low enough. the resulting inductors either become physically large, or the resistive loss in the winding affects efficiency. next we examine the input capacitor. we use 0.1 f here as well. at 150 khz, the 0.1 f capacitor has a reactance of about 10 . this reactance shunts away 90% of the noise current from the lisn, leaving only about 10% to the input. so 12 vp-p must be reduced to about 12 mvp-p (half the noise appears on each line terminal relative to ground). the differential inductor must have a reactance of about 1000 . at 150 khz the needed inductance is about 10 mhy. this can be split into two small chokes, one in each line, so that some common mode noise is also attenuated. 2 x 4.7 uhy was used. the selected inductors have about 5.5 of dc resistance, so i 2 r loss is relatively low. the inductors have a self-resonance in the 2 to 5 mhz range. this is a common mode resonance that can cause some trouble. it is damped by placing a resistor across each inductor. self-resonance is frequently stated on inductor datasheets, or it can be measured. the resistor value used is the same as the inductor impedance at resonance: equation 8 the resistor has no effect on the rest of the filter at lower frequencies - it's swamped by the lower impedance of the inductor.
AN4129 circuit description and design guidance doc id 023314 rev 1 27/39 4.13 emi filter and dimming 4.13.1 damping the input filter when the unit is dimmed a large transient voltage appears on the filter input capacitor: figure 33. undamped input filter waveforms with triac dimmer to maintain triac holding current, the ringing must be damped. the best way to do this is to add an r-c network across the filter output, where the network impedance is highest. ideally, the input current waveform should look like this: figure 34. properly damped waveforms actually, some high-frequency ringing can be tolerated, if the current reversal time is less than the turn-off time of the triac, about 20 microseconds. the input filter, however, would ring at about: equation 9 so current reversal time would be in the 70 microsecond range. damping is required. the filter's output impedance is high, the impedance at the line end is low. in fact, the line end of the network is much less than the 100 of the lisn at the ringing frequency, almost
circuit description and design guidance AN4129 28/39 doc id 023314 rev 1 insignificant for the damping function. so the ringing network primarily consists of the filter inductor and the converter input capacitor. the typical damping network across a current-sink load would consist of a capacitor and a resistor in series. the minimum capacitor value would be 3 times the filter capacitance (3x c1, use 0.33 f), and a resistor of: equation 10 however, power dissipation in the damping resistor can be a problem. if the dimmer is set to 90 degrees conduction, the input voltage comes on at the peak of the line waveform. the damping resistor must charge the damping capacitor 120 times a second to the peak line voltage. for each transient, the energy dissipated in the resistor is slightly less than: equation 11 other damping mechanisms exist, however, so the damping network does not need to be so large. reducing the size of the capacitor would allow the use of a 1/2 w resistor. the pfc-flyback converter, unlike a regulating converter, has a positive input resistance near the filter's resonant frequency. the input current it draws increases when the line voltage increases, short term. this contributes some damping. the effective resistance can be calculated from line voltage and input power. input power is about 11 w. at nominal line the input resistance is: equation 12 note that this resistance rises and falls as the square of the line voltage. some additional damping is provided by the winding resistance of the inductors and the fusible resistor. it was found experimentally that the ringing could be completely damped with a series r-c network of 0.22 f and 390 . the final filter design is shown below: figure 35. final input filter design !-v ' ' ' ' & x) & x) & x) / p+\ 5 5 2kpv)xvleoh / p+\ 7r&rqyhuwhu ,qsxw 5 . 5 .
AN4129 circuit description and design guidance doc id 023314 rev 1 29/39 the transient input waveforms are shown below: figure 36. input transient at 200 ma/div, 2.5 ms/div figure 37. input transient at 500 ma/div, 500 s/div figure 38. input transient at 1 a/div, 50 s/div where: yellow = triac dimmed line voltage magenta = line current, scale below.
circuit description and design guidance AN4129 30/39 doc id 023314 rev 1 the rather high current spike at the leading edge is due to the input capacitor charging thru the fusible resistor. a small inductor may be added to soften this if space permits, but it does no harm. even if triac dimming is not required the damper should be used. the emi filter can ring up the supply voltage to very high levels at turn-on if it is not present, and instability has been seen without the damper under normal operating conditions. 4.14 emi plot the conducted emissions plots for the two input lines are virtually identical. only one is shown below. the plot is the maximum of 10 scans for peak power. figure 39. conducted emi, peak hold for 10 scans 4.15 startup figure 40. cold startup, input and led currents where: yellow (not shown) = line voltage, triggers scope magenta = line current green = led current.
AN4129 circuit description and design guidance doc id 023314 rev 1 31/39 the unit produces usable light in about 0.1 seconds, and nearly full output in about 0.2 seconds. the vast majority of the startup time is the charging of the output filter capacitor (c11) to the led threshold voltage - reduced startup time can be traded off against increased led ripple current if faster startup is required. 4.16 component stress 4.16.1 thermal the unit was mounted above the bench in free air with the narrow end (ac input) down. temperatures were recorded after 45 minutes of operation. the dimmed temperatures were taken with a triac dimmer feeding the unit. the dimmer was adjusted to the point where the power analyzer reported the greatest loss. undimmed input voltage was 121 v. dimmed input voltage was 115 vrms, conduction angle about 150 degrees. efficiency measured 85.4%, loss measured 1.667 w. 4.16.2 electrical the scope image below was taken at 120 v input with an 18 led load. the trigger was set to pick up only the highest voltage, which occurs near the peak of each half cycle. table 1. temperatures after 45 minutes in free air measured point undimmed dimmed ambient 23.5 23.4 r1 41.5 50.3 r2 38.9 51.3 br1 38.1 48 l2, l3 43 46.4 u1 58.7 63.1 t1 50.2 54.7 d3 51.6 53.5 c11 38.7 39.3
circuit description and design guidance AN4129 32/39 doc id 023314 rev 1 figure 41. voltage and current stress yellow = fet drain voltage blue = fet current, 0.5 a per division. note the headroom available. the 800 v rating of the hvled815pf is unnecessary for 120 v applications. 4.17 extensions and modifications 4.17.1 lower output vo ltage, higher current the unit was designed for 18 leds, but it can easily be modified to drive 9. the transformer has two secondary windings that are connected in series on the demonstration board. if the foil is cut between the secondary side center pins, and the outside pin pairs connected, the secondary voltage is halved. the current regulating circuitry now sees a different turns ratio, and correctly regulates at twice the load current. some other changes must also be made if this is done: change snubber capacitor c10 to a high-quality part of four times the value, such as a 1200 pf cog ceramic rated for 200 v. change diode d3 to a 150 v schottky type such as st's stps1150 to reduce voltage drop. efficiency is reduced it this change is not made. change the output capacitor to one having 4 times the capacitance and half the voltage rating, 1200 f at 35 v. this maintains the ripple current near the same percentage as the original. if a preload resistor is used, change it to one having ? the original resistance. 4.17.2 emi filt er alternatives a second pattern was included on the pc board to allow experiments with a different filter configuration. a common mode filter may be needed in some applications, but it requires the damping network to be re-tuned. a small cm choke (such as wurth, part number 750311897) does a better job of suppressing common mode noise. this inductor type has another feature - the differential mode inductance is relatively high and stable, simplifying the damper design.
AN4129 circuit description and design guidance doc id 023314 rev 1 33/39 differential mode inductance (leakage inductance) can be measured (if it's not specified) by simply shorting one winding of the cm choke and measuring the other. the damper resistor and filter capacitors can then be re-tuned to work with it. 4.17.3 higher line voltage this is almost a wide-range design, dimmable at 90 v - 130 v, and operable from 90 v to 305 v. the only thing preventing this is the voltage rating of capacitors and the output diode. the hvled815pf's internal fet is rated for 800 v, a good design margin for european 230 v lines and us 277 v lighting circuits. the design is not sensitive to input frequency. if the ac injection divider is adjusted, reasonable harmonic performance can be expected from 180 v to 305 v. at higher input voltage the surge limiting resistor should be coordinated with the single-cycle surge rating of the input bridge. triac dimming at higher input voltage requires a redesign of the input filter. dimming at 10 w on a 230 v line may not be possible using only the damper described.
bill of materials AN4129 34/39 doc id 023314 rev 1 5 bill of materials table 2. bom designator description manufacturer br1 bridge smt diodes inc rh06-t c2, c3 0.1 f 250 v panasonic ecq-e2104kb c4 0.22 f 250 v panasonic ecq-e2224kb c5 1 nf 0805 x7r c6 4.7 f 25 v taiyo yuden tmk212bj475kg-t c7 10 nf 0805 x7r c8 10 f 35 v nichicon upw1v100mdd6 c9 2200 pf ?y? murata de2e3kh222ma3b c10 330 pf avx 12062a331jat2a c11 330 f 63 v panasonic eeu-fc1j331 d1 bat48zfilm st bat48zfilm d2 mmsd4148 mmsd4148 d3 stth102a st stth102a l2, l3 4.7 mhy wurth 744 772 472 r1 10 fusible vishay/bc components lnfr0100001009jr500 r2 390 0.5 w vishay nfr25h0003900jr500 r3 270 k 1206 5% r4 3.0 k 0805 5% r5 1r00 1% 1206 1% r6 16 k 0805 5% r7 2.4 k 0805 5% r8, r10 10 k 1206 5% r9 43 k 0805 5% t1 csm 2010 -180 cramer csm 2010 -180
AN4129 transformer specifications doc id 023314 rev 1 35/39 6 transformer specifications figure 42. transformer specifications for 18-led load !-v
pc layout AN4129 36/39 doc id 023314 rev 1 7 pc layout figure 43. top placement figure 44. top copper figure 45. bottom placement figure 46. bottom layer
AN4129 references doc id 023314 rev 1 37/39 8 references 1. st altair05t-800 datasheet, ?off-line all-primary-sensing switching regulator?, rev1. 2. st db1534: evlaltair05t-5w data brief, ?altair05t-800 5 w wide range cv-cc optoless adapter demonstration board?, rev1. 3. st hvled805 datasheet, ?off-line led driver with primary-sensing?, rev2. 4. st an3360 application note, ?3.2 w led power supply based on hvled805?, rev2. 5. st hvled815pf datasheet, ?off-line led driver with primary-sensing?, rev3. 6. us patent 5,729,443 ?switched current regulator with improved power switch control mechanism? pavlin (1998). 7. us patent 7,978,485 ?thyristor power control circuit with damping circuit maintaining thyristor holding current? stamm et al. (2011). 8. st an1059 application note, ?design equations of high-power-factor flyback converters based on the l6561?, rev1. 9. st an2711 application note, ?120 vac input-triac dimmable led driver based on the l6562a?, rev3. 10. st an2838 application note, ?35 w wide-range high power factor flyback converter demonstration board using the l6562a?, rev2. 11. st an4130 application note, ?steval-ill045v1: 120 v a19 dimmable high power factor 9 w led driver using hvled815pf?, rev1.
revision history AN4129 38/39 doc id 023314 rev 1 9 revision history table 3. document revision history date revision changes 29-oct-2012 1 initial release.
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